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STP80NF5508 Datasheet:
Ultra Low Dropout300 mV at 300-mA Load Ultra Low Noise30 mVRMS (10-Hz to 100-kHz) Shutdown Control 130-mA Ground Current at 300-mA Load 1.5% Guaranteed Output Voltage Accuracy 400-mA Peak Output Current Capability Uses Low ESR Ceramic Capacitors Fast Start-Up (50 ms) Fast Line and Load Transient Response (v 30 ms) 1-mA Maximum Shutdown Current Output Current Limit Reverse Battery Protection Built-in Short Circuit and Thermal Protection
STP80NF5508 Suppliers:
Non-inductive. Thermally enhanced Industry standard TO220 package. RoHS compliant. Low thermal resistance, 5.9 C/W resistor hot spot to metal tab. Complete thermal flow design available for easy implementation. Superior vibration durability. Small thin package for high density PCB installation.
STP80NF5508 On stock:
be used to gate data to the output pins, inde- pendent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) isequal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27C64A has a standby mode which reduces the active current from 30mA to 100µA. The M27C64A is placed in the standby mode by apply- ing a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. Two Line Output Control Because EPROMs are usually used in larger mem- ory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system
50-mA Low-Dropout Regulator Available in 1.5-V, 1.8-V, 2.5-V, 2.8-V, 3.0-V Output Noise Typically 56 µVRMS (TPS79030) Only 17 µA Quiescent Current at 50 mA 1 µA Quiescent Current in Standby Mode Dropout Voltage Typically 57 mV at 50 mA (TPS79030) Over Current Limitation C40C to 125C Operating Junction Temperature Range 5-Pin SOT-23 (DBV) Package
The Lock-detect circuitry connect to the output of the phase dector ciruits and is used to disable the transmit- ter when the VCO is not phase-locked to the reference oscillator. This is necessary to avoid unwanted out- of-band transmission and to provide compliance with regulatory limits during an unlocked condition. Pin 15 (LD) is used to set the threshold of the lock-detect circuit. A shunt capacitor is used to set an RC time con- stant with an on-chip eries 1KΩ resistor. The time constant should be approximately 15 times the reference period.
Maximum frequency of operation is limited by power dissipation due to high- voltage switching, gate charge, and bias power. Figure 5 indicates the maximum switching frequency as a function of input voltage and gate charge. For higher ambient temperatures, the switching frequency should be derated linearly.
NOTES 1Best Fit between codes 25 and 230. INL is very layout sensitive. 2Due to linearity mismatch in dual ramps. 3Measured from rising edge of clock to transition of Codes 0 to 255. 4Minimum pulse width (at 20 MHz) limited by rise time. Pulse width for Code 25 will be greater when CLOCK < 20 MHz. 5Output load = 10 pF and 2 mA source/sink. 6Load conditions to test output drive capability. Linearity will degrade with either capacitive or current loading. Best linearity obtained driving a single CMOS input. 7All performance specifications valid when supply maintained at +5 V, 5%. 8Tested from +4.75 V to +5.25 V.
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